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CAT93C46
1-Kb Microwire Serial EEPROM FEATURES
s High speed operation: 2MHz s 1.8V to 5.5V supply voltage range s Selectable x8 or x16 memory organization s Self-timed write cycle with auto-clear s Software write protection s Power-up inadvertant write protection s Low power CMOS technology s 1,000,000 Program/erase cycles s 100 year data retention s Industrial temperature ranges s RoHS-compliant 8-pin PDIP, SOIC, TSSOP and
DESCRIPTION
The CAT93C46 is a 1K-bit Serial EEPROM memory device which is configured as either 64 registers of 16 bits (ORG pin at VCC) or 128 registers of 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C46 features a self-timed internal write with auto-clear. On-chip PowerOn Reset circuit protects the internal logic against powering up in the wrong state.
For Ordering Information details, see page 13.
8-pad TDFN packages
PIN CONFIGURATION
PDIP (L) SOIC (V, X) TSSOP (Y) TDFN (VP2)
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG GND NC VCC CS SK
FUNCTIONAL SYMBOL
VCC
SOIC (W)
ORG
1 2 3 4 8 7 6 5 ORG GND DO DI
CS SK DI
CAT93C46
DO
GND
PIN FUNCTIONS
Pin Name CS SK DI DO VCC GND ORG NC Function Chip Select Clock Input Serial Data Input Serial Data Output Power Supply Ground Memory Organization No Connection
Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 organization is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization.
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc. No. 1106, Rev. F
1
CAT93C46
ABSOLUTE MAXIMUM RATINGS(1)
Storage Temperature Voltage on Any Pin with Respect to Ground
(2)
-65C to +150C -0.5 V to +6.5 V
RELIABILITY CHARACTERISTICS(3) Symbol NEND(4) TDR Parameter Endurance Data Retention Min 1,000,000 100 Units Program/ Erase Cycles Years
D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V, TA=-40C to +85C, unless otherwise specified.
Symbol ICC1 ICC2 ISB1 ISB2 ILI ILO VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16Mode) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Test Conditions fSK = 1MHz VCC = 5.0V fSK = 1MHz VCC = 5.0V VIN=GND or VCC, CS =GND ORG=GND VIN=GND or VCC, CS =GND ORG=Float or VCC VIN = GND to VCC VOUT = GND to VCC, CS = GND 4.5V VCC < 5.5V 4.5V VCC < 5.5V 1.8V VCC < 4.5V 1.8V VCC < 4.5V 4.5V VCC < 5.5V IOL = 2.1mA 4.5V VCC < 5.5V IOH = -400A 1.8V VCC < 4.5V IOL = 1mA 1.8V VCC < 4.5V IOH = -100A VCC - 0.2 2.4 0.2 -0.1 2 0 VCC x 0.7 Min Max 1 500 2 1 1 1 0.8 VCC + 1 VCC x 0.2 VCC+1 0.4 Units mA A A A A A V V V V V V V V
Notes: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC +0.5V. During transitions, the voltage on any pin may undershoot to no less than -1.5V or overshoot to no more than VCC +1.5V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Block Mode, VCC = 5V, 25C
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
2
Doc No. 1106, Rev. F
CAT93C46
PIN CAPACITANCE TA=25C, f=1MHz, VCC=5V Symbol COUT
(1)
Test Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG)
Conditions VOUT=0V VIN=0V
Min
Typ
Max 5 5
Units pF pF
CIN(1)
A.C. CHARACTERISTICS(2) VCC = +1.8V to +5.5V, TA=-40C to +85C, unless otherwise specified. Limits Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(1) tEW tCSMIN tSKHI tSKLOW tSV SKMAX Parameter CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency DC 0.25 0.25 0.25 0.25 2000 Min 50 0 100 100 0.25 0.25 100 5 Max Units ns ns ns ns s s ns ms s s s s kHz
POWER-UP TIMING (1)(3) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max 1 1 Units ms ms
NOTES: (1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (2) Test conditions according to "AC Test Conditions" table. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
3
Doc No. 1106, Rev. F
CAT93C46
A.C. TEST CONDITIONS Input Rise and Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages Output Load
50ns 0.4V to 2.4V 4.5V VCC 5.5V 0.8V, 2.0V 4.5V VCC 5.5V 0.2VCC to 0.7VCC 1.8V VCC 4.5V 0.5VCC 1.8V VCC 4.5V Current Source IOLmax/IOHmax; CL=100pF
DEVICE OPERATION
The CAT93C46 is a 1024-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C46 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 9-bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 10-bit instructions control the reading, writing and erase operations of the device. The CAT93C46 operates on a single power supply and will generate on chip the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status during a write operation. The serial communication protocol follows the timing shown in Figure 1. The ready/busy status can be determined after the start of internal write cycle by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy "1" into the DI pin. The DO pin will enter the high impedance state on the rising edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The Ready/Busy INSTRUCTION SET Address Instruction READ ERASE WRITE EWEN EWDS ERAL WRAL Start Bit 1 1 1 1 1 1 1 Opcode 10 11 01 00 00 00 00 x8 A6-A0 A6-A0 A6-A0
11XXXXX 00XXXXX 10XXXXX 01XXXXX
flag can be disabled only in Ready state; no change is allowed in Busy state. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit address (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organization). Read Upon receiving a READ command (Figure 2) and an address (clocked into the DI pin), the DO pin of the CAT93C46 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). Erase/Write Enable and Disable The CAT93C46 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C46 write and erase instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. The EWEN and EWDS instructions timing is shown in Figure 3.
Data x8 x16 Comments Read Address AN- A0 Clear Address AN- A0 D7-D0 D15-D0 Write Address AN- A0 Write Enable Write Disable Clear All Addresses D7-D0 D15-D0 Write All Addresses
Doc No. 1106, Rev. F
x16 A5-A0 A5-A0 A5-A0
11XXXX 00XXXX 10XXXX 01XXXX
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
4
CAT93C46
Figure 1. Sychronous Data Timing
tSKHI SK tDIS DI tCSS CS tDIS DO tPD0,tPD1 DATA VALID tCSMIN VALID VALID tDIH tSKLOW tCSH
Figure 2. Read Instruction Timing
SK tCSMIN CS STANDBY AN DI 1 1 0 tHZ 0 DN DN-- 1 D1 D0 HIGH-Z AN--1 A0
DO
HIGH-Z
tPD0
Figure 3. EWEN/EWDS Instruction Timing
SK
CS
STANDBY
DI
1
0
0
* * ENABLE=11 DISABLE=00
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
5
Doc No. 1106, Rev. F
CAT93C46
Write After receiving a WRITE command (Figure 4), address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking for auto-clear and data store cycles on the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46 can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into. Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN (Figure 5). The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/ busy status of the CAT93C46 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical "1" state. Figure 4. Write Instruction Timing
SK
Erase All Upon receiving an ERAL command (Figure 6), the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical "1" state. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN (Figure 7). The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/ busy status of the CAT93C46 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed.
tCSMIN CS AN DI 1 0 1 tSV DO HIGH-Z tEW BUSY READY HIGH-Z tHZ AN-1 A0 DN D0 STATUS VERIFY STANDBY
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
6
Doc No. 1106, Rev. F
CAT93C46
Figure 5. Erase Instruction Timing
SK
CS AN DI
STATUS VERIFY
AN-1
STANDBY
A0
tCS MIN
1
1
1
tSV
HIGH-Z DO
tHZ BUSY tEW READY
HIGH-Z
Figure 6. ERAL Instruction Timing
SK
CS
STATUS VERIFY
tCS MIN
STANDBY
DI
1
0
0
1
0
tSV tHZ BUSY tEW READY
HIGH-Z
DO
HIGH-Z
Figure 7. WRAL Instruction Timing
SK
CS
STATUS VERIFY tCSMIN
STANDBY
DI
1
0
0
0
1
DN
D0 tSV tHZ BUSY tEW READY HIGH-Z
DO
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
7
Doc No. 1106, Rev. F
CAT93C46
8-LEAD 300 MIL PLASTIC DIP (L)
E1
E D
A2
A
A1
L
e b2 b
eB
SYMBOL A A1 A2 b b2 D E E1 e eB L
MIN 0.38 3.05 0.36 1.14 9.02 7.62 6.09 7.87 0.115
NOM
MAX 4.57 3.81 0.56 1.77 10.16 8.25 7.11 9.65 0.150
24C16_8-LEAD_DIP_(300P).eps
0.46
7.87 6.35 2.54 BSC 0.130
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MS001. 3. Dimensioning and tolerancing per ANSI Y14.5M-1982
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
8
Doc No. 1106, Rev. F
CAT93C46
8-LEAD 150 MIL SOIC (V, W)
E1 E
D
h x 45 C A 1
e b
A1 L
SYMBOL A1 A b C D E E1 e h L 1
MIN 0.10 1.35 0.33 0.19 4.80 5.80 3.80
NOM
MAX 0.25 1.75 0.51 0.25 5.00 6.20 4.00
1.27 BSC 0.25 0.40 0 0.50 1.27 8
24C16_8-LEAD_SOIC.eps
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MS-012.
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
9
Doc No. 1106, Rev. F
CAT93C46
8-LEAD 208 MIL SOIC (X)
E
b
D A e A1 L
c
1
SYMBOL A1 A b c D E E1 e L 1
MIN 0.05 0.36 0.19 5.13 7.75 5.13
NOM
MAX 0.25 2.03 0.48 0.25 5.33 8.26 5.38
1.27 BSC 0.51 0 0.76 8
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: 1. All dimensions are in millimeters. 2. Complies with EIAJ specification EDR-7320. 3. D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions and gate burrs shall not exceed 0.06in per side. 4. E1 does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 0.010in per side. 5. Lead span/stand off height/coplanarity are considered as special characteristic (A1).
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
10
Doc No. 1106, Rev. F
CAT93C46
8-LEAD TSSOP (Y)
D
8 5
SEE DETAIL A
c
E
E1
E/2
1
4
GAGE PLANE
PIN #1 IDENT. 1 A2 L 0.25
SEATING PLANE SEE DETAIL A
A
e b
A1
SYMBOL A A1 A2 b c D E E1 e L 1
MIN 0.05 0.80 0.19 0.09 2.90 6.30 4.30 0.50 0.00
NOM
MAX 1.20 0.15 1.05 0.30 0.20 3.10 6.50 4.50 0.75 8.00
0.90
3.00 6.4 4.40 0.65 BSC 0.60
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MO-153
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
11
Doc No. 1106, Rev. F
CAT93C46
8-PAD TDFN 2X3 PACKAGE (VP2)
A
E
PIN 1 INDEX AREA
D
A1
A2 A3
D2
SYMBOL A A1 A2 A3 b D D2 E E2 e L
MIN 0.70 0.00 0.45 0.20 1.90 1.30 2.90 1.20 0.20
NOM 0.75 0.02 0.55 0.20 REF 0.25 2.00 1.40 3.00 1.30 0.50 TYP 0.30
MAX 0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 0.40
b e 3xe E2
PIN 1 ID
L
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MO-229.
TDFN2X3 (03).eps
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
12
Doc No. 1106, Rev. F
CAT93C46
EXAMPLE OF ORDERING INFORMATION
Prefix CAT Device # 93C46 V Suffix I -G T3
Optional Company ID
Product Number 93C46
Temperature Range I = Industrial (-40C - 85C)
Tape & Reel(4) T: Tape & Reel 2: 2000/Reel 3: 3000/Reel
L V W X Y VP2
Package = PDIP = SOIC, JEDEC = SOIC, JEDEC = SOIC, EIAJ = TSSOP = TDFN (2X3mm)
Lead Finish(2) Blank: Matte-Tin G: NiPdAu
Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish for the SOIC, EIAJ (X) package is Matte-Tin; the standard lead finish for all other packages is NiPdAu. (3) The device used in the above example is a CAT93C46VI-GT3 (SOIC, JEDEC, Industrial Temperature, NiPdAu, Tape & Reel). (4) The SOIC, EIAJ (X) package is available in reels of 2000 pcs/reel (i.e. CAT93C46XI-T2). All other packages are offered in reels of 3000 pcs/reel. (5) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
13
Doc No. 1106, Rev. F
CAT93C46
REVISION HISTORY
Date 12/01/05 12/08/05 02/22/06 Revision Comments A B C Initial Issue Update D.C Operating Characteristics Update Pin Configuration Update A.C. Charateristics, Die Rev N Update Package Dimensions Update Ordering Information Update Package Marking Update Pin Configuration Update Pin Functions Update D.C. Operating Charateristics Update A.C. Charateristics Update Device Operation Update Package Marking Remove Tape and Reel Update Example of Package Information Update D.C. Operating Charateristics UpdateTest Condition for Pin Capacitance Update A.C. Charateristics Update Device Operation Add 8 Lead 208 mil SOIC (X) Package Update Package Marking Update Example of Package Information Update D.C. Operating Characteristics Update A.C. Characteristics Update Figures 5 and 6 Remove Package Marking
05/24/06
D
08/01/06
E
02/08/07
F
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
14
Doc No. 1106, Rev. F
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Publication #: Revison: Issue date:
1106 E 02/08/07

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